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esmt/emp EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 1/26 4-channel power management ic for portable devices general description the EMQ8932 is a high efficiency, 4-channel power management ic for portable devices application. it integrates a complete linear charger for single cell lithium-ion battery, a linear regulator and two high efficiency step-down dc/dc converters. the linear charger (ch1) operates from 4.25v to 5.5v input voltage and up to 1a charging capability. it is thermal regulated and specifically designed to work within usb power specifications. the linear regulator (ch2) features ultra-high power supply rejection ratio (75db at 1khz), low output voltage noise (30v), low dropout voltage (270mv), low quiescent current (110a) and fast transient response. it operates from 2.5v to 5.5v input voltage, up to 600ma loading capability and regulates adjustable output voltage from 1.2v to 5.0v. the two synchronous buck converters (ch3, ch4) operate from 2.5v to 5.5v input voltage, up to 600ma loading capability and regulate adjustable output voltage from 0.6v to vin. it features low quiescent current, fixed 1.5mhz internal frequency operation. the EMQ8932 is available in tqfn24 4x4 package, it is green compliant (rohs and halogen-free). features linear charger 4.25v to 5.5v input voltage programmable charge current up to 1a thermal regulation maximizes charge rate without risk of overheating act as a ldo when battery is removed preset 4.2v charge voltage with 1% accuracy automatic recharge charge status indicator c/10 charge termination battery reverse leakage current less than 1a 45a shutdown supply current soft-start limits inrush current linear regulator 1.2v to 5.0v output voltage 75db typical psrr at 1khz 30v rms output voltage noise (10hz to 100khz) 270mv typical dropout at 600ma two synchronous buck converters 0.6v to vin output voltage up to 95% efficiency low dropout operation: 100% duty cycle no schottky diode needed shutdown current < 1a (ch1-ch4) independent enable pin(ch1-ch4) independent input voltage pin(ch1-ch4) no external compen sation network needed excellent line and load transient response(ch1-ch4) over current protection over temperature protection applications hand-held instruments portable information applications wireless networking gps mp3/mp4/pmp multi-media
esmt/emp EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 2/26 figure 1. typical application
esmt/emp EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 3/26 connection diagram tqfn24 4x4 order information EMQ8932-00hc24nrr 00 adjustable output voltage hc24 tqfn-24 package nrr rohs & halogen free rating: -40 to 85c package in tape & reel order, mark & packing information package product id marking packing tqfn-24 EMQ8932-00hc24nrr 3 k units tape & reel
esmt/emp EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 4/26 terminal functions terminal name no. i/o description run3 1 i ch3 enable input. gnd3 2 - ground. fb3 3 i ch3 voltage feedback pin. vin1 4 i ch1 positive input supply voltage. gnd1 5 - ground. bat 6 o ch1 charge current output and battery voltage feedback. nc 7 - non-connection pin. prog 8 ch1 charge current program pin, i bat =(v prog /r prog )*960 the prog pin must not be directly shorted to ground at any condition. mchrg 9 i ch1 open-drain charge status output. shdn2 10 i ch2 enable input. vin2 11 i ch2 input voltage. out 12 o ch2 output voltage feedback. adj2 13 i ch2 adjustable negative feedback control. gnd2 14 - ground. cc 15 i ch2 compensation capacitor. fb4 16 i ch4 voltage feedback pin. gnd4 17 - ground. run4 18 i ch4 enable input. vin4 19 i ch4 input voltage. vss_pwr4 20 - ground. sw4 21 o ch4 switch pin. must be connected to inductor. sw3 22 o ch3 switch pin. must be connected to inductor. vss_pwr3 23 - ground. vin3 24 i ch3 input voltage.
esmt/emp EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 5/26 function block diagram
esmt/emp EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 6/26 absolute maximum ratings supply input voltage -0.3v to 6.0v (vin, vin2, vin3, vin4) bat pin voltage -0.3v to 6.0v mchrg pin voltage -0.3v to 6.0v prog pin voltage -0.3v to 6.0v sw3 switch pin voltage -0.3v to (vin3+0.3v) sw4 switch pin voltage -0.3v to (vin4+0.3v) other i/o pin voltage -0.3v to (vin+0.3v) storage temperature -65c to +150c power dissipation 1.85w esd susceptibility hbm ---------------- 2kv mm --------------- 200v junction temperature 150c thermal resistance ja (tqfn24 4x4) 45 c/w operating ratings temperature range -40c Q t a Q 85c vin supply voltage 4.25v Q v dd Q 5.5v supply voltage 2.5v Q v dd Q 5.5v (vin2, vin3, vin4) electrical characteristics apply for v in =5.0v, v in2 = v out2 +1v (note 6), v en2 = v in2 , c in2 = c out2 = 2.2f, c cc2 = 33nf, v in3 = 3.6v, v in4 = 3.6v and t a = 25c ( unless otherwise noted), boldface limits apply for the operating temperature extremes: -40c and 85c. EMQ8932 symbol parameter conditions min typ max units ch1 v in input voltage 4.25 5.5 v charge mode, r prog =10k (note 4) 260 standby mode (charge terminated) 106 i cc input supply current shutdown mode (r prog not connected, v in esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 7/26 voltage v in from high to low 30 mv i term c/10 termination current threshold r prog =10k 0.1 ma/ma v prog prog pin voltage r prog =10k, current mode 1.0 v i chgb chgb pin weak pull-down current v chgb =5v 24 a v chgb chgb pin output low voltage i chgb =5ma 0.23 v v rechrg recharge battery threshold voltage v float -v rechrg 160 mv t ilm junction temperature in constant temperature mode 120 o c r on power fet ?on? resistance 450 m t ss soft-start time i bat =0 to i bat =960v/r prog 100 s t recharge recharge comparator filter time v bat high to low 2.4 ms t term termination comparator filter time i bat falling below i chg /10 1.1 ms i prog prog pin pull-up current 0.4 a ch2 (note 8) v in2 input voltage 2.5 5.5 v -2 +2 v otl2 output voltage tolerance 100a i out2 300ma v out2 (nom) +0.5v vin2 5.5v (note 5) adj2=v out2 -3 +3 % of v out (nom) v out2 output adjust range 1.20 5.0 v i out2 maximum output current average dc current rating 600 ma i limit2 output current limit 600 950 ma i out2 = 0ma 110 supply current i out2 = 600ma 255 i q2 shutdown supply current v out2 = 0v, en2 = gnd 0.001 1 a i out2 = 50ma 19 i out2 = 300ma 110 v do2 dropout voltage (note 5) i out2 = 600ma 230 mv line regulation i out2 = 1ma, (v out2 + 0.5v) v in2 5.5v (note 6) -0.1 0.02 0.1 %/v v ou2t load regulation 100a i out2 600ma 0.001 %/ma
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 8/26 e n2 output voltage noise i out2 = 10ma, 10hz f 100khz 30 v rms v ih , (v out + 0.5v) v in 5.5v (note 8) 1.2 ven2 en2 input threshold v il , (v out + 0.5v) v in 5.5v (note 8) 0.4 v i en2 en2 input bias current en2 = gnd or vin 0.1 100 na i adj2 adj2 input leakage adj2=1.3v (note 7) 0.1 3 na t sd thermal shutdown temperature (note 8) 165 t sd_hyst thermal shutdown hysteresis 30 t on2 start-up time c out2 = 10f, v out2 at 90% of final value 80 s ch3 (note 8) i vfb3 feedback current 30 na t a = 25c 0.588 0.600 0.612 v fb3 regulated feedback voltage ?40c t a 85c 0.585 0.600 0.615 v v fb3 reference voltage line regulation v in3 = 2.5v to 5.5v 0.4 %/v v ovl3 output over-voltage lockout v ovl3 = v ovl3 ? v fb3 20 50 80 mv output voltage line regulation v in3 = 2.5v to 5.5v 0.4 %/v v out3 output voltage load regulation 0.5 % i pk3 peak inductor current v in3 = 3v, v fb3 = 0.5v or v out3 = 90%, duty cycle < 35% 1.0 a quiescent current (note 9) v fb3 = 0.5v or v out3 = 90% 200 340 a i q3 shutdown v en3 = 0v, v in3 = 4.2v 0.1 1 a v fb3 = 0.6v or v out3 = 100% 1.2 1.5 1.8 mhz f osc3 oscillator frequency v fb3 = 0v or v out3 = 0v 290 khz r pfet3 r ds(on) of pmos i sw3 = 100ma 0.45 0.55 r nfet3 r ds(on) of nmos i sw3 = ?100ma 0.40 0.5 i sw3 sw3 leakage v en3 = 0v, v sw3 = 0v or 5v, v in3 = 5v 1 a v en3 en3 threshold 0.5 1.3 v i en3 en3 leakage current 1 a ch4 (note8) i vfb4 feedback current 30 na
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 9/26 t a = 25c 0.588 0.600 0.612 v v fb4 regulated feedback voltage ?40c t a 85c 0.585 0.600 0.615 v fb4 reference voltage line regulation v in4 = 2.5v to 5.5v 0.4 %/v v ovl4 output over-voltage lockout v ovl4 = v ovl4 ? v fb4 20 50 80 mv output voltage line regulation v in4 = 2.5v to 5.5v 0.4 %/v v out4 output voltage load regulation 0.5 % i pk4 peak inductor current v in4 = 3v, v fb4 = 0.5v or v out4 = 90%, duty cycle < 35% 1.0 a quiescent current (note 9) v fb4 = 0.5v or v out4 = 90% 200 340 a i q4 shutdown v en4 = 0v, v in4 = 4.2v 0.1 1 a v fb4 = 0.6v or v out4 = 100% 1.2 1.5 1.8 mhz f osc4 oscillator frequency v fb4 = 0v or v out4 = 0v 290 khz r pfet4 r ds(on) of pmos i sw4 = 100ma 0.45 0.55 r nfet4 r ds(on) of nmos i sw4 = ?100ma 0.40 0.5 i sw4 sw4 leakage v en4 = 0v, v sw4 = 0v or 5v, v in4 = 5v 1 a v en4 en4 threshold 0.5 1.3 v i en4 en4 leakage current 1 a note 1: absolute maximum ratings indicate limits beyond which damage may occur. electrical specifications do not apply when operatin g the device outside of its rated operating conditions. note 2: all voltages are with respect to the potential at the ground pin. note 3: maximum power dissipation for the device is calculated using the following equations: ja a t - j(max) t d p = where tj(max) is the maximum junction temper ature, ta is the ambient temperature, and ja is the junction-to-ambient thermal resistance. note 4: ch1 supply current includes prog pin current (approximately 100 a) but does not include any current delivered to the battery through the bat pin (approximately 96ma). note 5: ch2 does not apply to input voltages below 2.5v since this is the minimum input operating voltage. note 6: ch2 dropout voltage is measured by reducing v in until v out drops 100mv from its nominal value at v in -v out = 0.5v. dropout voltage does not apply to the regulator versions with v out less than 2.5v. note 7: ch2 the adj2 pin is disconnected internally for the preset versions. note 8: ch2, ch3 and ch4 build-in internal over-temperatu re protection to prevent over-load condition. note 9: dynamic quiescent current is higher due to the gate charge delivered at the switching frequency.
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 10/26 typical performance characteristics v in =5.0v, v in2 = v out2 (nom) + 1v, c in2 = c out2 = 2.2f, c cc = 33nf, v en2 = v in2 , v en3 = v in3 , c in3 =4.7f, l 3 =2.2h, c out3 =4.7f, c in4 =4.7f, l 4 =2.2h, c out4 =4.7f, v en4 = v in4 t a = 25c, unless otherwise specified ch1 regulated output (float) voltage vs temperature ch1 charge current vs battery voltage ch1 charge current vs supply voltage ch1 charge current vs ambient temperature ch1 regulated output (float) voltage vs supply voltage ch1 chgb pin i-v curve (strong pull-down state) i bat (ma) v bat (v) i bat (ma) vin (v) v bat =4v thermal regulation temperature ( o c) i bat (ma) v bat =4v v float (v) temperature ( o c) v float (v) vin (v) v bat =4v i chgb (ma) v chgb (v)
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 11/26 ch1 load transient (battery removed) ch1 line transient (battery removed) ch1 chgb pin current vs temperature (strong pull-down state) ch1 chgb pin i-v curve (weak pull-down state) ch1 chgb pin current vs temperature (weak pull-down state) ch1 trickle charge current vs temperature v prog =0.2v, i bat =2ma~150ma 400 s/div v bat (50mv/div) i bat (100ma/div), tr=tf=20 s v prog =0.2v, i bat =4ma v bat (50mv/div) vin (v), tr=tf=5 s 400 s/div 5.5 4.5 temperature ( o c) i chgb (ma) v bat =4v v chgb =1v v bat =4.3v i chgb ( a) v chgb (v) temperature ( o c) i chgb ( a) v bat =4.3v v chgb =5v i trickle (ma) temperature ( o c) v bat =2.5v r prog =2k
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 12/26 ch1 trickle charge current vs supply voltage ch1 trickle charge threshold vs temperature ch1 recharge voltage threshold vs temperature ch1 regulated output (float) voltage vs charge current v in (v) v bat =2.5v r prog =2k i trickle (ma) v trickle (v) temperature ( o c) r prog =10k v rechrg (v) temperature ( o c) r prog =10k r prog =1.25k v float (v) i bat (ma)
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 13/26 ch2 psrr vs. frequency ch2 psrr vs. frequency ch2 psrr vs. frequency ch2 psrr vs. frequency ch2 psrr vs. frequency ch2 supply current vs. load current load current (ma) psrr (db) frequency (hz) psrr (db) frequency (hz) psrr (db) frequency (hz) psrr (db) frequency (hz) psrr (db) frequency (hz) supply current (a)
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 14/26 ch2 dropout voltage vs. load current ch2 supply current vs. input voltage input voltage (v) ch2 enable and disable ch2 power down response ch2 power up response ch2 load transient 400 s/div dropout voltage (mv) load current (ma) supply current (a) 50mv/div 100ma/div v out (1v/div) v shdn (2v/div) v out (1v/div) v shdn (2v/div)
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 15/26 ch2 load transient 400 s/div ch2 line transient 200 s/div ch2 line transient 200 s/div ch2 current limit 50mv/div 200ma/div v out =3.3v, i out =10ma v out (10mv/div) 4.3v 5.3v vin v out =3.3v, i out =600ma v out (10mv/div) 4.3v 5.3v vin i out (200ma/div)
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 16/26 ch3/ch4 efficiency vs output current ch3/ch4 efficiency vs output current ch3/ch4 output voltage vs load current ch3/ch4 efficiency vs output current ch3/ch4 efficiency vs output current ch3/ch4 reference voltage vs temperature
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 17/26 ch3/ch4 r ds(on) vs temperature ch3/ch4 dynamic supply current vs temperature ch3/ch4 oscillator freq uency vs temperature ch3/ch4 r ds(on) vs input voltage ch3/ch4 dynamic supply current vs supply voltage ch3/ch4 oscillator frequency vs supply voltage
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 18/26 ch3/ch4 discontinuous operation ch3/ch4 load step ch3/ch4 load step ch3/ch4 start-up from shutdown ch3/ch4 load step ch3/ch4 load step i load 500ma/div i l 500ma/div v in =3.6v 20 s/div v out =1.8v i load =100ma to 600ma v in =3.6v 1 s/div v out =1.8v i load =50ma i l 200ma/div sw 2v/div v out 10mv/div ac coupled run 5v/div v out 1v/div v in =3.6v 40 s/div v out =1.8v i load =600ma (3 resistor) i l 500ma/div v out 100m/div ac coupled i l 500ma/div v in =3.6v 20 s/div v out =1.8v i load =0ma to 600ma i load 500ma/div v out 100m/div ac coupled i l 500ma/div i load 500ma/div v in =3.6v 20 s/div v out =1.8v i load =50ma to 600ma v out 100m/div ac coupled i load 500ma/div v out 100m/div ac coupled i l 500ma/div v in =3.6v 20 s/div v out =1.8v i load =200ma to 600ma
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 19/26 application information the EMQ8932 is a high efficiency, 4-channel power management ic for portable devices application. the four channels are listed as following ch1 linear charger for single cell lithium-ion battery ch2 high psrr, low noise, low dropout 600ma ldo ch3/4 600ma synchronous buck converters ch2/3/4 are vout adjustable ch1 linear charger ch1 the linear charger is a complete linear charger for single cell lithium-ion battery that is specifically designed to work within usb power specifications. no external sense resistor and blocking diode are required. charging current can be programmed externally with a single resistor. the built-in thermal regulation facilitates charging with maximum power without risk of overheating. the charger always preconditions the battery with 1/10 of the programmed charge current at the beginning of a charge cycle, until 40 s after it verifies that the battery can be fast-charged. the charger automatically terminates the charge cycle when the charge current drops to 1/10th the programmed value after the final float voltage is reached. the charger can also be used as a ldo when battery is removed. other features include reverse current protection, shutdown mode, charge current monitor, under voltage lockout, automatic recharge and status indicator. ? ch1 programming charging current the charging current (i bat ) can be programmed up to 1.0a by equation (1). i bat =(v prog /r prog )*960?????????????(1) ch2 high psrr, low noise, low dropout 600ma ldo the ldo adopts the classical regulator topology in which negative feedback control is used to perform the desired voltage regulating function. the negative feedback is formed by using feedback resistors (r3, r4) to sample the output voltage (v out2 ) for the non-inverting input of the error amplifier, whose inverting input is set to the bandgap reference voltage. by virtue of its high open-loop gain, the error amplifier operates to ensure that the sampled output feedback voltage at its non-inverting input is virtually equal to the preset bandgap reference voltage. the error amplifier compares the voltage difference at its inputs and produces an appropriate driving voltage to the p-channel mos pass transistor to control the amount of current reaching the output. if there are changes in the output voltage due to load changes, the feedback re sistors register such changes to the non-inverting input of the error amplifier. the error amplifier then adjusts its driving voltage to maintain virtual short between its two input nodes under all loading conditions. in a nutshell, the regulation of the output voltage is achieved as a direct result of the erro r amplifier keeping its input voltages equal. this negative feedback control topology is further augmented by the shutdown, the temperature protection and current protection circuitry. ? ch2 output voltage control the ldo allows direct user control of the output voltage in accordance with the amount of negative feedback present. to see th e explicit relationship between the output voltage and the negative feedback, it is convenient to conceptualize the ldo as an ideal non-inverting operational amplifier with a fixed dc reference voltage v ref2 at its non-inverting input. such a conceptual representation of the ldo in closed-loop configuration is shown in figure 2. this ideal op amp
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 20/26 features an ultra-high input resistance such that its inverting input voltage is virtually fixed at v ref2 . the output voltage is therefore given by: ? ? ? ? ? ? + = 1 3 r 4 r ref2 v out2 v ............................................(2) this equation can be rewritten in the following form to facilitate the determination of the resistor values for a chosen output voltage: ? ? ? ? ? ? ? = 1 1.19v out2 v 3 r 4 r ..................................................(3 ) set r3 equal to 100k to optimize for overall accuracy, power supply reje ction, noise, and power consumption. v in v out r 1 r 2 v ref + - ? ch2 output capacitor the ldo is specially designed for use with ceramic output capacitors of as low as 2.2f to take advantage of the savings in cost and space as well as the superior filtering of high frequency noise. capacitors of higher value or other types may be used, but it is important to make sure its equivalent series resistance (esr) be restricted to less than 0.5 . the use of larger capacitors with smaller esr values is desirable for applications involving large and fast input or output transients, as well as for situations where the application systems are not physically located immediately adjacent to the battery power source. typical ceramic capa citors suitable for use with the ldo are x5r and x7r. the x5r and the x7r capacitors are able to maintain their capacitance values to within 20% and 10%, respectively, as the temperature increases. ? ch2 no-load stability the ldo is capable of stable operation during no-load conditions, a mandatory feature for some applications such as cmos ram keep-alive operations. ? ch2 input capacitor a minimum input capacitance of 1f is required for the ldo. the capacitor value may be increased without limit. improper workbench set-ups may have adverse effects on the normal operation of the regulator. a case in point is the instability that may result from long supply lead inductance coupling to the output through the gate capacitance of the pass transistor. this will establish a pseudo lcr network, and is likely to happen under high current conditions or near dropout. a 10f tantalum input capacitor will dampen the parasitic lcr action thanks to its high esr. however, cautions should be exercised to avoid regulator short-circuit damage when tantalum capacitors are used, for they are prone to fail in short-circuit operating conditions. ? ch2 compensation (noise bypass) capacitor substantial reduction in the output voltage noise of the ldo is accomplished th rough the connection of the noise bypass capacitor c cc (33nf optimum) between cc pin and the ground. because cc pin connects directly to the high impedance output of the bandgap reference circuit, the level of the dc leakage currents in the c cc capacitors used will adversely reduce the regulator output voltage. this sets the dc leakage level as the key selection criterion of the c cc capacitor types for use with the figure 2. simplified regulator topology r 4 r 3 v out2
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 21/26 ldo. npo and cog ceramic capacitors typically offer very low leakage. although the use of the c cc capacitors does not affect the transient response, it does affect the turn-on time of the regulator. tradeoff exists between output noise level and turn-on time when selecting this capacitor value. ? ch2 power dissipation and thermal shutdown thermal overload results from excessive power dissipation that causes the ic junction temperature to increase beyond a safe operating level. the ldo relies on dedicated thermal shutdown circuitry to limit its total power dissipation. an ic junction temperature t j exceeding 165c will trigger the thermal shutdown logic, turning off the p-channel mos pass transistor. the pass transistor turns on again after the junction cools off by about 30c. when continuous thermal overload conditions persist, this thermal shutdown action then results in a pulsed waveform at the output of the regulator. the concept of thermal resistance ja (c/w) is often used to describe an ic junction?s relative readiness in allowing its thermal energy to dissipate to its ambient air. an ic junction with a low thermal resistance is preferred because it is relatively effective in dissipating its thermal energy to its ambient, thus resulting in a relatively low and desirable junction temperature. the relationship between ja and t j is as follows: t j = ja (pd) + t a ........................................................ (4) t a is the ambient temperature, and p d is the power generated by the ic and can be written as: p d = i out (v in - v out ) .................................................... (5) as the above equations show, it is desirable to work with ics whose ja values are small such that t j does not increase strongly with p d . to avoid thermal overloading the ldo, refrain from exceeding the absolute maximum junction temperature rating of 150c under continuous operating conditions. overstressing the regulator with high loading currents and elevated input-to-output differential voltages can increase the ic die temperature significantly. ? ch2 shutdown ch2 enters the sleep mode when the en2 pin is low. when this occurs, the pass transistor, the error amplifier, and the biasing circuits, including the bandgap reference, are turned off, thus reducing the supply current to typically 1na. such a low supply current makes the ldo best suited for battery-powered applications. the maximum guaranteed voltage at the en2 pin for the sleep mode to take effect is 0.4v. a minimum guaranteed voltage of 1.2v at the en2 pin would activate the ldo. direct connection of the en2 pin to the v in2 to keep the regulator on is allowed for the ldo. in this case, the en2 pin must not exceed the supply voltage v in2 . ? fast start-up fast start-up time is important for overall system efficiency impr ovement. the ldo assures fast start-up speed when using the optional noise bypass capacitor (c cc ). to shorten start-up time, the ldo internally supplies a 500a current to charge up the capacitor until it reaches about 90% of its final value. ch3/4 600ma synchronous buck converters the typical application circuit of the current mode dc/dc converters is shown in fig.4.
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 22/26 ? ch3/4 inductor selection basically, inductor ripple current and core saturation are two factors considered to decide the inductor value. ? ? ? ? ? ? ? ? ? ? = in v out v out v l i 1 1 l f ................................. (6) the eq. 6 shows the inductor ripple current is a function of frequency, inductance, vi n (v in3 , v in4 ) and v out (v out3 , v out4 ). it is recommended to set ripple current to 40% of max. load current. a low dcr inductor is preferred. ? ch3/4 c in and c out selection a low esr input capacitor can prevent large voltage transients at vi n (v in3 , v in4 ). the rms current of input capacitor is required larger than i rms calculated by: () in out in out v v v v omax i rms i ? ? ...............?. (7) esr is an important parameter to select c out (c out3 , c out4 ). the output ripple v out ( v out3 , v out4 ) is determined by: ? ? ? ? ? ? ? ? ? ? + ? out c f 8 1 l i out v esr ...............?..?(8) higher values, lower cost ceramic capacitors are now available in smaller sizes. these ceramic capacitors have high ripple currents, high voltage ratings and low esr that make them ideal for switching regulator applications. optimize very low output ripple and small circuit size is doable from c out selection since c out does not affect the internal control loop stability. it is recommended to use the x5r or x7r which have th e best temperature and voltage characteristics of all the ceramics for a given value and size. ? ch3/4 output voltage (v out3 , v out4 ) the output voltage can be determined by following equation: ? ? ? ? ? ? ? ? + = 5 r 6 r 1 v out v 6 . 0 .................................??....?(9) ch3 case, replace r 5 as r 7 , r 6 as r 8 in ch4 case. ? ch3/4 thermal considerations although thermal shutdown is build-in in the step-down dc/dc converter(s) that protects the device from thermal damage, the total power dissipation that the converter(s) can sustain should be base on the package thermal capability. the formula to ensure the safe operation is shown in note 3. to avoid the dc/dc converter(s) from exceeding the maximum junction temperature, the user will need to do some thermal analysis. ? ch3/4 guidelines for pcb layout to ensure proper operation of the dc/dc converter(s) , please note the following pcb layout guidelines: 1. the gnd trace, the sw (sw3, sw4) trace and the v in (v in3 , v in4 ) trace should be kept short, direct and wide. 2. v fb (fb3, fb4) pin must be connected directly to the feedback resistors. resistive divider r 5 /r 6 (ch3); r 7 /r 8 (ch4) must be connected and parallel to the output capacitor c out (c out3 , c out4 ). 3. the input capacitor c in (c in3 , c in4 ) must be fig. 3 v out 2.7v sw fb v in run gnd 2.2 uh 22 pf c out 10uf cer v in 3.3 ? 5.5v c in 4.7 uf cer r6 (350k ) r5 (100k ) run
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 23/26 connected to pin v in (v in3 , v in4 ) as closely as possible. 4. keep sw (sw3, sw4) node away from the sensitive v fb (fb3, fb4) node since this node is with high frequency and voltage swing. 5. keep the (?) plates of c in (c in3 , c in4 ) and c out (c out3 , c out4 ) as close as possible. ? ch3/4 design example assume the step-down dc/dc converter(s) is (are) used in a single lithium-ion battery-powered application. the v in ( v in3 , v in4 ) range will be about 2.7v to 4.2v. output voltage (v out3 , v out4 ) is 1.8v. with this information we can calculate l using equation: ? ? ? ? ? ? ? ? ? ? = in v out v out v l i 1 1 l f ..........................?(10) substituting v out = 1.8v, v in = 4.2v, i l = 240ma and f = 1.5mhz in eq. 10 gives: h 86 . 2 1 240ma 1.5mhz 1.8v l = ? ? = ? ? ? ? ? ? 4.2v 1.8v ...........?(11 ) a 2.2 h inductor could be chose with this application. a greater inductor with less equivalent series resistance makes best efficiency. c in (c in3 , c in4 ) will require an rms current rating of at least i load(max) /2 and low esr. in most cases, a ceramic capacitor will satisfy this requirement.
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 24/26 tqfn-24 4x4x0.75mm outline dimension common dimensions millimeter dimensions inch symbol min. nom. max. min. nom. max. a 0.700 0.750 0.800 0.027 0.029 0.031 a3 0.195 0.203 0.211 0.0077 0.0080 0.0083 b 0.180 0.230 0.300 0.007 0.009 0.012 d 3.925 4.000 4.075 0.154 0.157 0.160 e 3.925 4.000 4.075 0.154 0.157 0.160 e 0.50 bsc 0.020 bsc l 0.300 0.350 0.400 0.012 0.014 0.016 d2/e2 2.50/2.50 2.65/2.65 2.80/2.80 0.098/0.098 0.104/0.104 0.110/0.110
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 25/26 revision history revision date description 1.0 2008.05.30 original 1.1 2008.12.08 correct pin order of mchrg and shdn2 in page 4. 1.2 2009.05.26 modify order information 1.3 2010.10.13 modify packing quantity for tape and reel
esmt/emp preliminary EMQ8932 elite semiconductor memory technology inc. / elite micropower inc. publication date : oct. 2009 revision : 1.3 26/26 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without th e prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publicatio n. esmt assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the application of ou r products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellectual property rights of thir d parties which may result from its use. no license, either express , impl ied or otherwise, is granted under any patents, copyrights or other inte llectual property ri ghts of esmt or others. any semiconductor devices may have inherently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized fo r use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage . if products described here are to be used for such kinds of applic ation, purchaser must do its own quality assurance testing appropriate to such applications.

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